Our proposed dummy-less open bit-line scheme can save approximately 4% of the array height. To solve these problems, we propose a novel sensing circuit that can operate effectively even under unbalanced bit-line capacitance, thus suggesting the possibility of an open bit-line scheme without dummy bit-lines. Thus, the sensing operation of a conventional BLSA with this unbalanced bit-line capacitance experiences various problems: sensing voltage decrease, data flipping, and asymmetric equalization. This strategy causes the conventional bit-line sense amplifiers (BLSAs) in the MATs located at both ends of the cell array block to have a much smaller complementary bit-line capacitance than a true bit-line capacitance. To reduce the area overhead, one edge MAT can be eliminated by converting the dummy bit-lines of the other edge MAT into real bit-lines. In a conventional open bit-line scheme of DRAM, the edge subarrays (MATs) located at both ends of the cell array block contain alternated real and dummy bit-lines, unavoidably leading to an additional area overhead. Index Terms-DRAM, charge-transferred presensing (CTPS), negatively-driven sensing(NDS), free-level precharged bitline(FLPB), sense amplifier offset voltage, threshold voltage distribution. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip. The negative voltage of NDS scheme is about -0.3V to -0.6V. The sense amplifier takes a negative voltage during the sensing and amplifying period. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The negatively-driven sensing (NDS) scheme enhances the NMOS amplifying ability. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with free-level precharged bitline (FLPB) scheme is adopted.
0 kommentar(er)
